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cy7c199d 256 k (32 k 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05471 rev. *i revised june 2, 2011 256 k (32 k 8) static ram features temperature ranges ? ?40 c to 85 c pin and function compatible with cy7c199c high speed ? t aa = 10 ns low active power ? i cc = 80 ma at 10 ns low cmos standby power ? i sb2 = 3 ma 2.0 v data retention automatic power-down when deselected complementary metal oxide semiconductor (cmos) for optimum speed/power transistor-transistor logic (ttl) compatible inputs and outputs easy memory expansion with ce and oe features available in pb-free 28-pin 300-mil-wide molded small outline j-lead package (soj) and 28-pin thin small outline package (tsop) i packages functional description the cy7c199d is a high performance cmos static ram organized as 32,768 words by 8-bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ) and tri-state drivers. this device has an automatic power-down feature, re ducing the power consumption when deselected. the input and output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low and we low). write to the device by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 14 ). read from the device by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins appears on the i/o pins. logic block diagram i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 [+] feedback
cy7c199d document number: 38-05471 rev. *i page 2 of 14 contents pin configuration ............................................................. 3 selection guide ................................................................ 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 switching characteristics ................................................ 6 data retention characteristics ....................................... 7 data retention waveform ................................................ 7 switching waveforms ...................................................... 7 truth table ........................................................................ 9 ordering information ........................................................ 9 ordering code definitions ..... ...................................... 9 package diagrams .......................................................... 10 acronyms ........................................................................ 12 document conventions ................................................. 12 units of measure ....................................................... 12 document history page ................................................. 13 sales, solutions, and legal information ...................... 14 worldwide sales and design s upport ......... .............. 14 products .................................................................... 14 psoc solutions ......................................................... 14 [+] feedback
cy7c199d document number: 38-05471 rev. *i page 3 of 14 pin configuration figure 1. 28-pin soj (top view) figure 2. 28-pin tsop i (top view) selection guide description -10 (industrial) unit maximum access time 10 ns maximum operating current 80 ma maximum cmos standby current 3ma 22 23 24 25 26 27 28 1 2 4 7 8 9 13 12 11 10 14 17 16 15 5 6 18 21 20 19 a 0 ce i/o 7 oe a 1 a 2 a 3 a 4 i/o 6 i/o 5 i/o 4 we v cc a 5 a 6 a 7 a 10 a 11 a 12 a 13 i/o 1 i/o 2 gnd i/o 3 a 8 a 14 i/o 0 a 9 3 tsop i top view (not to scale) 1 2 3 4 5 6 7 8 9 11 14 15 16 20 19 18 17 21 24 23 22 12 13 25 28 27 26 v cc we a 4 a 5 a 6 a 7 a 8 a 9 a 3 a 2 a 1 a 10 a 11 a 12 a 13 a 14 i/o 2 gnd i/o 3 i/o 4 i/o 7 ce a 0 oe i/o 0 i/o 5 i/o 6 i/o 1 10 [+] feedback
cy7c199d document number: 38-05471 rev. *i page 4 of 14 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied .... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc to relative gnd [1] ................................?0.5 v to +6.0 v dc voltage applied to outputs in high z state [1] ................................ ?0.5 v to v cc + 0.5 v dc input voltage [1] ............................. ?0.5 v to v cc + 0.5 v output current into outputs (low) ............................. 20 ma static discharge voltage ........................................ > 2,001 v (per mil-std-883, method 3015) latch-up current ................................................... > 140 ma operating range range ambient temperature v cc speed industrial ?40 ? c to +85 ? c5 v ? 0.5 v 10 ns electrical characteristics over the operating range parameter description test conditions cy7c199d-10 unit min max v oh output high voltage i oh = ?4.0 ma 2.4 ? v v ol output low voltage i ol = 8.0 ma ? 0.4 v v ih input high voltage [1] 2.2 v cc + 0.5 v v il input low voltage [1] ?0.5 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 a i cc v cc operating supply current v cc = v cc(max) , i out = 0 ma, f = f max = 1/t rc 100 mhz ? 80 ma 83 mhz ? 72 ma 66 mhz ? 58 ma 40 mhz ? 37 ma i sb1 automatic ce power-down current? ttl inputs v cc = v cc(max) , ce > v ih , v in > v ih or v in < v il , f = f max ?10ma i sb2 automatic ce power-down current? cmos inputs v cc = v cc(max) , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v, f = 0 ?3ma note 1. v il(min) = ?2.0 v and v ih(max) = v cc + 1 v for pulse durations of less than 5 ns. [+] feedback
cy7c199d document number: 38-05471 rev. *i page 5 of 14 capacitance parameter [2] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 5.0 v 8 pf c out output capacitance 8pf thermal resistance parameter [2] description test conditions 28-pin soj 28-pin tsop i unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 59.16 54.65 ? c/w ? jc thermal resistance (junction to case) 40.84 21.49 ? c/w ac test loads and waveforms figure 3. ac test loads and waveforms [3] r2 r1 480 ? 3.0 v gnd 90% 10% 90% 10% 5 v output 5pf including all input pulses * capacitive load consists of all components of the test environment 30 pf* output z = 50 ? 50 ? 1.5 v (a) (c) high z characteristics: 255 ? jig and scope (b) rise time: ?? 3 ns fall time: ?? 3 ns notes 2. tested initially and after any design or process changes that may affect these parameters. 3. ac characteristics (except high z) are tested using the load conditions shown in figure 3 (a). high z characteristics are tested for all speeds using the test load shown in figure 3 (c). [+] feedback
cy7c199d document number: 38-05471 rev. *i page 6 of 14 switching characteristics over the operating range parameter [4] description cy7c199d-10 unit min max read cycle t power [5] v cc(typical) to the first access 100 ? ? s t rc read cycle time 10 ? ns t aa address to data valid ? 10 ns t oha data hold from address change 3 ? ns t ace ce low to data valid ? 10 ns t doe oe low to data valid ? 5 ns t lzoe [6] oe low to low z 0 ? ns t hzoe [6, 7] oe high to high z ? 5 ns t lzce [6] ce low to low z 3 ? ns t hzce [6, 7] ce high to high z ? 5 ns t pu [8] ce low to power-up 0 ? ns t pd [8] ce high to power-down ? 10 ns write cycle [9, 10] t wc write cycle time 10 ? ns t sce ce low to write end 7 ? ns t aw address setup to write end 7 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 7?ns t sd data setup to write end 6 ? ns t hd data hold from write end 0 ? ns t hzwe [6] we low to high z ? 5 ns t lzwe [6, 7] we high to low z 3 ? ns notes 4. test conditions assume signal transition time of 3 ns or less for all speeds, timing reference levels of 1.5 v, input pulse l evels of 0 to 3.0 v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 5. t power gives the minimum amount of time that the power supply should be at typical v cc values until the first memory access can be performed. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. t hzoe , t hzce , and t hzwe are specified with c l = 5 pf as in part (b) of figure 3 on page 5 . transition is measured ? 200 mv from steady-state voltage. 8. this parameter is guaranteed by design and is not tested. 9. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input setup and hold timing should be refe renced to the rising edge of the signal that terminates the w rite. 10. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback
cy7c199d document number: 38-05471 rev. *i page 7 of 14 data retention characteristics over the operating range parameter description conditions min max unit v dr v cc for data retention 2.0 ? v i ccdr data retention current v cc = v dr = 2.0 v, ce > v cc ? 0.3 v, v in > v cc ? 0.3 v or v in < 0.3 v ?3ma t cdr [11] chip deselect to data retention time 0 ? ns t r [12] operation recovery time 15 ? ns data retention waveform switching waveforms figure 4. read cycle no. 1: address transition controlled [13, 14] figure 5. read cycle no. 2 oe controlled [14, 15] 4.5 v 4.5 v t cdr v dr > 2 v data retention mode t r ce v cc address data out previous data valid data valid t rc t aa t oha 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd data out oe ce v cc supply current impedance icc isb high notes 11. tested initially and after any design or proc ess changes that may affect these parameters. 12. full device operation requires linear v cc ramp from v dr to v cc(min) > 50 s or stable at v cc(min) > 50 s. 13. device is continuously selected. oe , ce = v il . 14. we is high for read cycle. 15. address valid prior to or coincident with ce transition low. [+] feedback
cy7c199d document number: 38-05471 rev. *i page 8 of 14 figure 6. write cycle no. 1: ce controlled [16, 17, 18] figure 7. write cycle no. 3 we controlled, oe low [18, 19] switching waveforms (continued) t wc t aw t sa t ha t hd t sd t sce data in valid we data i/o address ce t hd t sd t lzwe t sa t ha t aw t wc t hzwe note 20 data io address ce we data in valid notes 16. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input setup and hold timing should be referenced to the rising edge of the signal that terminat es the write. 17. data i/o is high impedance if oe = v ih . 18. if ce goes high simultaneously with we high, the output remains in a high-impedance state. 19. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 20. during this period the i/os are in the output state and input signals should not be applied. [+] feedback
cy7c199d document number: 38-05471 rev. *i page 9 of 14 ordering code definitions truth table ce we oe inputs/outputs mode power h x x high z deselect/power-down standby (i sb ) l h l data out read active (i cc ) l l x data in write active (i cc ) l h h high z deselect, output disabled active (i cc ) ordering information cypress offers other versions of this type of product in many different configurations and features. the following table contai ns only the list of parts that are currently available. for a comple te listing of all options, visit the cypress website at http://www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution center s, manufacturer's representatives and distributors. to find th e office closest to you, visit us at http://www.cypress.com/ go/datasheet/offices. speed (ns) ordering code package diagram package type operating range 10 CY7C199D-10VXI 51-85031 28-pin (300-mil) molded soj (pb-free) industrial cy7c199d-10zxi 51-85071 28-pin tsop type i (pb-free) please contact your local cypress sales repr esentative for availability of these parts. temperature grade: i i = industrial pb-free package type: v or z v = 28 pin (300-mil) molded soj z = 28 pin tsop type 1 speed grade: 10 ns process technology: 90 nm bus width = 8 density = 256 k fast sram family technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c 71 d-xxx x 9 9 cy i [+] feedback
cy7c199d document number: 38-05471 rev. *i page 10 of 14 package diagrams figure 8. 28-pin soj 300-mils v28.3 (molded soj v21) 51-85031 *d [+] feedback
cy7c199d document number: 38-05471 rev. *i page 11 of 14 figure 9. 28-pin tsop type 1 (8 13.4 1.2 mm) z28 (standard) package diagrams (continued) 51-85071 *i [+] feedback
cy7c199d document number: 38-05471 rev. *i page 12 of 14 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable soj small outline j-lead sram static random access memory tsop thin small outline package ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius a micro amperes s micro seconds ma milli amperes mm milli meter ns nano seconds pf pico farad vvolts wwatts [+] feedback
cy7c199d document number: 38-05471 rev. *i page 13 of 14 document history page document title: cy7c199d, 256 k (32 k 8) static ram document number: 38-05471 revision ecn orig. of change submission date description of change ** 201560 swi see ecn advance information datasheet for c9 ipp *a 233728 rkf see ecn dc parameters modified as per eros (spec # 01-02165) pb-free offering in ordering information *b 262950 rkf see ecn removed 28-lcc pinout and package diagrams added data retention characteristics table added t power spec in switching characteristics table shaded ordering information *c 307594 rkf see ecn reduced speed bins to -10, -12 and -15 ns *d 820660 vkn see ecn converted from preliminary to final removed 12 ns and 15 ns speed bin removed commercial operating range removed ?l? part removed 28-pin pdip and 28-pin soic package changed overshoot spec from v cc +2v to v cc +1v in footnote #2 changed i cc spec from 60 ma to 80 ma for 100 mhz speed bin added i cc specs for 83 mhz, 66 mhz and 40 mhz speed bins updated thermal resistance table updated ordering information table *e 2745093 vkn see ecn included 28-pin soic package changed v ih level from 2.0v to 2.2v for industrial grade, changed t sd from 5 ns to 6 ns, and t hzwe from 6 ns to 5 ns included automotive-e information *f 2897087 aju 03/22/10 removed obsolete pa rts from ordering information table updated package diagrams *g 3023234 rame 09/06/2010 added auto-e soic package related info changed tdoe spec from 10 ns to 11 ns in cy7c199d-25. added ordering code definitions . added acronyms and document conventions . *h 3130763 pras 01/07/11 dislodged automotive in formation to a new datasheet (001-65530) *i 3271782 pras 06/02/2011 updated functional description (removed ?for best practice recommendations, refer to the cypress ap plication note an1064, sram system guidelines.?). updated package diagrams . updated in new template. [+] feedback
document number: 38-05471 rev. *i revised june 2, 2011 page 14 of 14 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c199d ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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